1. Fields of the Invention
The present invention relates to an adaptive data-retention-voltage regulating system for static random-access memory (SRAMs), especially to an adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) that reduces leakage power by using power gating. Moreover, data-retention-voltage is dynamically regulated according to process, voltage and temperature (PVT) variations. Thus leakage power of the SRAM at the stand-by mode is significantly decreased. By using dynamic regulation mechanism of closed-loop, the virtual supply voltage is maintained at data-retention-voltage. Without causing data loss, the leakage power is reduced more.
2. Descriptions of Related Art
SRAM is for storage of various information. SRAM generally consists of three main architectural blocks: a SRAM cell array, a peripheral circuit including address decoder/Y pass, amplifier, write circuit etc., and an I/O circuit. A basic unit of the SRAM cell array is a memory cell composed of two p-type metal oxide semiconductor (PMOS) load transistors, two n-type metal oxide semiconductor (NMOS) driver transistors and two NMOS access transistors. The memory cells are arranged in an array. Moreover, low-power design plays an important role in electronics (portable devices, wireless sensor network, WSN, bio-electronics, etc.) since energy conservation has become a universal concern. However, SRAM inside electronics typically occupies large area in a System-on-a-chip (SoC) and accounts for system static power dissipation/leakage power.
In order to reduce leakage power at standby mode, lowering the supply voltage to data-retention-voltage (DRV) is a common and effective way. The Data Retention Voltage (DRV) is the minimum standby voltage at which an SRAM array can preserve its data. That is the supply voltage at which the Static Noise Margin (SNM) of the SRAM cell in standby mode reduces to zero. With the design of Advanced Process, DRV increases with process variation. This causes a challenge for voltage scaling mechanism and leakage power reduction. Moreover, the variations of DRV are larger than the conventional process. In order to deal with worst case, the SRAM cell tends to have higher DRV and the leakage power remains the same. For example, data-retention-voltage of each SRAM Cell is different due to impact of process, voltage and temperature (PVT) variations on DRV. In order to make all data in SRAM hold under VDD scaling, the normal operation voltage of SRAM should be higher than the maximum DRV of memory cells of SRAM. However, at the design stage, there is no way to learn all the conditions of the chip. Thus the worst case should be taken into consideration while determining the normal operation voltage at the standby mode. This cause the whole memory cells of SRAM have higher DRV. Under such condition, the leakage power remains high. Furthermore, the probability of the worst case is quite low during operation of the SRAM. Thus most of the time, the normal operation voltage at the standby mode is able to be reduced.
Refer to Taiwanese Pat. Pub. No. 201037720 “integrated circuit structure”, an integrated circuit structure includes an active power supply line, a data-retention power supply line, a first memory macro and a second memory macro. The first and the second memory macros are connected to the active power supply line and the data-retention power supply line. Each memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. A low leakage current mode control pin is coupled to the switch. The switch connects the active power supply line and the data-retention power supply line to the memory cell array according to a signal of the low leakage current mode control pin. Thereby the voltage of the data-retention power supply is generated by a voltage generator while the voltage generator is outside the memory macro. Thus the voltage generator can be designed into a complicated circuit. The memory reduces the leakage current without sacrificing the data availability. However, while in use, the voltage generator generates normal operation voltage at the standby mode by voltage converters such as dc-dc converters or linear regulators while the conversion efficiency of the voltage converter is not ideal. The voltage converters lead to additional power consumption and conversion time of the system. The scaling of the normal operation voltage also lowers the conversion efficiency of the voltage generator. Thus there is a power loss and the voltage conversion takes longer time. From the point of view of the system, the above design is unable to achieve higher reduction of the leakage power. Moreover, the conventional techniques uses external data retention power for voltage supply and the external data retention power is not so sensitive to PVT variations. Thus the memory reduces the leakage current without sacrificing the data availability. The normal supply voltage of the memory at the standby mode is a fixed value. The change of the DRV can't be regulated dynamically when the DRV is changed due to impact of certain variations (such as voltage or temperature variations) that change with time.